By Kay A. Robbins
This publication examines the problems correct to the layout of vector and pipelined desktops utilizing the Cray X-MP/24. the aim of the ebook is to assist the readers arrive at a deep realizing of the way vector processing structures fairly paintings. those insights could be invaluable to the scientist who wish to receive greatest functionality from a vector laptop, to the pc technological know-how scholar, and to the compiler author. The e-book can be used to complement a standard textbook in a graduate or senior point direction in desktop structure. The booklet appears on the total layout of the Cray X-MP after which explores the operation of the computing device by way of targeted timings of varied directions and code segments. It examines such matters as guide concerns and buffering, dealing with of bounce directions, use of registers to carry intermediate effects, reminiscence conflicts as a result of vectorization, optimum vectorization of a number of assertion loops, and synchronization issues of multi-tasking. precise Gantt charts are supplied to lead the reader during the timing issues.
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Extra info for The Cray X-MP/Model 24: A Case Study in Pipelined Architecture and Vector Processing
8. 5 i l l u s t r a t i n g a l i n e c o n f l i c t . 9. 5. 5. Bidirectional Memory Access Bidirectional Memory Access Because of the complicated arbitration scheme described above, it is possible that one vector operation may be performed before one which was issued previously. In addition there is no hardware check for dependencies in the data for memory locations accessed. This can lead to unexpected inconsistencies and must be controlled by the programmer. 6 Delays c a n c a u s e u n e x p e c t e d inconsistencies Suppose that ADAT is an address located in Bank 0 and BDAT occurs 6 words later.
Since the Cray X-MP has two input ports and one output port, it allows essentially one vector operation with two source operations and one result to be performed at a time. We can introduce a functional unit conflict into the above example by replacing the multiplication and integer addition by floating addition. The timing results for the two code segments are 3852 clock cycles and 3843 clock cycles respectively. Here the functional unit conflict is the major factor in determining the overall loop execution time.
You can often use these messages as a guide in writing more vectorizable code. Automatic vectorization on a larger scale than loops is difficult and is the subject of much current research. The impact of memory conflicts on vectorization is described in Chapter 6 and scheduling of loops is addressed in Chapter 7. 6 M e m o r y Access The effect of memory references on instruction timings is complicated by the conflict resolution scheme used on the Cray X-MP. In this chapter we will discuss the memory organization and look at the timings for memory operations in some detail.